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Leti’s approach to 3D stacking of transistors starts with a conventionally built and locally-interconnected bottom layer of transistors, which are then covered with a top layer of transistors built using relatively low-temperature processes branded as “Cool Cube.” Figure 1 shows a simplified cross-sectional schematic of a Cool Cube stack of transistors and interconnects.
Cool Cube M3D does not transfer a layer of built devices as in the approach using TSV, but instead transfers just a nm-thin layer of homogenous semiconducting material for subsequent device processing.
The reason that completed transistors are not transferred in the first place is because of intrinsic alignment issues, which are eliminated when transistors are instead fabricated on the same wafer.
“We have lots of data to prove that alignment precision is as good as can be seen in 2D lithography, typically 3nm,” explained Maud Vinet, Leti’s advanced CMOS laboratory manager in an exclusive interview with 95% of the silicon bulk from the backside.
To achieve very shallow adiabatic heating the toolset needs to ramp up in less than 100 nsec.
In order to get strong absorption in the top surface, shorter wavelengths are useful, less than 800 nm.
“Laser non-equilibrium heating is enabling technology for 3D devices,” affirmed Steve Moffatt, chief technology officer, Front End Products, Applied Materials.
Now that Qualcomm has endorsed Cool Cube M3D as a preferred approach to CMOS: CMOS transistor stacking in the near-term, we may assume that R&D in novel unit-processes has mostly concluded.
Leti’s trick to overcome this thermal-budget issue is to use pre-amorphizing implants (PAI) to completely dis-order the silicon before transfer and then solid-phase epitaxy (SPE) post-transfer to grow device-grade single-crystal silicon at ~500°C.
Since neither aluminum nor copper interconnects can withstand this temperature range, the interconnects for the bottom layer of transistors need to be tungsten wires with the highest melting point of any metal but somewhat worse electrical resistance (R).
This entry was posted on Friday, April 17th, 2015 at am and is filed under News Stories, Top Stories .
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M3D Roadmaps Leti shows data that M3D transistor stacking can provide immediate benefit to industry by combining two 28nm-node CMOS layers instead of trying to design and manufacture a single 14nm-node CMOS layer: area gain 55%, performance gain 23%, and power gain 12%.